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RS latch with VHDL

I have wrote a simple RS latch with VHDL and tried to synthesis it with ISE. The synthesizer added a D flip flop where the D input is grounded and my (S)et and (R)eset inputs are treated as preset and clear inputs. I expected to see NAND gates only. Why it added a flip flop while there is no need for that? Also why the D input is connected to ground? 

entity rs is
Port ( r : in  STD_LOGIC;
       s : in  STD_LOGIC;
       q : inout  STD_LOGIC);
end rs;

architecture Behavioral of rs is
begin
 process( r, s )
 begin
    if r = '1' then
        q <= '0';
    elsif s = '1' then
        q <= '1';
    else
        q <= q;
    end if;
 end process;
end Behavioral;

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Solution

  • Your observation that a flip flop has been used is not correct. The element is labelled ldcp, and this is a transparent latch. Looking at your code, a latch is what you have described. The D input is connected to ground, because all your process ever does is set or clear the latch; you have not described a 'load' operation, so the latch does not use its D input.