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verilogcomparison-operatorsmux

Comparing two numbers without comparison operators in verilog

Two 8-bit inputs are fed to the comparator, and if first one is greater than second, they are supposed to be subtracted, else they are supposed to be added. But, > and < operators aren't supposed to be used to compare them. So, I have written my logic as:

input[7:0] in1,in2;
output select;
assign select=(in1-in2)?0:1;

It is always subtracting, unless difference equals 0. If I use division, 0 cannot be an input or my program can crash. Any suggestions on how to solve this problem?

Thanks a lot for your time.

Solution

  • Remember that the leftmost bit of a negative number is aways 1. So you can use it to check the sign of the difference.

    input[7:0] in1,in2;
output select;
wire [7:0] difference = in1-in2;
wire sign_of_difference = difference[7];
assign select = sign_of_difference? 0:1;