VHDL Error : Choice in CASE statement alternative must be locally static

Question

My requirement is to compare the two array values using case statement. So I am using a for loop for all iterations.

Both are Input arrays : Memory_in array(expression) values are compared with sorted_array(choice) array values and Shaped_data is the output array (case statements).

I am getting static case error for my code below:

process (clk)

variable in_array:     sorted;  
   variable out_array:     sorted;      
begin
  -- in_array := sorted_array;
    if rising_edge(clk) then
        for i in 0 to 15 loop 
            case (Memory_in(i)) is
          when sorted_array(0) => out_array(i) := x"F";
          when sorted_array(1) => out_array(i) := x"E";
          when sorted_array(2) => out_array(i) := x"D";
          when sorted_array(3) => out_array(i) := x"C";
          when sorted_array(4) => out_array(i) := x"B";
          when sorted_array(5) => out_array(i) := x"A";
          when sorted_array(6) => out_array(i) := x"9";
          when sorted_array(7) => out_array(i) := x"8";
          when sorted_array(8) => out_array(i) := x"7";
          when sorted_array(9) => out_array(i) := x"6";
          when sorted_array(10) => out_array(i) := x"5";
          when sorted_array(11) => out_array(i) := x"4";
          when sorted_array(12) => out_array(i) := x"3";
          when sorted_array(13) => out_array(i) := x"2";
          when sorted_array(14) => out_array(i) := x"1";
          when sorted_array(15) => out_array(i) := x"0";
          when others  => null;--out_array(i) := "ZZZZ";
     end case;
          end loop;
   Shaped_Data <= out_array;
       end if;
end process;

The logic can be implemented using if else statement also but case statement would require less hardware. So I thought case statement would be better.

Is this error because of i value ? how do i do this ?

Answer 1

Whenever you find a big but regular structure, you can usually exploit that regularity. In this case, it simply means another loop.

What you have written reduces to something very like this:

process (clk)
   variable out_array:     sorted;      
begin
  -- in_array := sorted_array;
    if rising_edge(clk) then
        for i in 0 to 15 loop 
            for j in 0 to 15 loop
                if Memory_in(i) = sorted_array(j) then
                    out_array(i) := 15 - j; -- maybe via type conversion
                end if;
            end loop;
        end loop;
        Shaped_Data <= out_array;
    end if;
end process;