I'm trying to change the mapping of a library primative from unisim to unifast in my design, but only for simulation purposes. I want to specify the configuration at the testbench level.
My design hierarchy looks something like this:
entity m1_chip_tb is
end m1_chip_tb;
architecture behavioral of m1_chip_tb is
...
m1: entity work.m1_chip
m1_clocks: entity work.clock_logic_m1
mmcm_pix: MMCME2_ADV
All the examples for doing VHDL configurations (including the ones on Xilinx's site) that I've been able to find seem to assume the configuration applies to a entity instantiated locally. But I need a configuration that drills down from the top testbench level.
Here's what I've tried using:
configuration cfg_xilinx of m1_chip is
for rtl
for m1:clock_logic_m1
use entity work.clock_logic_m1(rtl);
for rtl
for all:MMCME2
use entity unifast.MMCME2;
end for;
end for;
end for;
end for;
end cfg_xilinx;
But I get an error "Cannot find component declaration" on the m1: line
Incidentally, the entire design is written using instantiation by entity with the exception of the MMCME2_ADV instantiation.
I'd appreciate any suggestions for how to properly specify the hierarchy in the configuration definition.
(As a point of clarification, I have the unisim libary specified in the clock_logic_m1.vhd file. I'm trying to override that for my simulations); i.e.:
library unisim;
use unisim.vcomponents.all;
You cannot use configuration with direct instantiation - that is the main drawback. However, if you don't insist on using configuration for the control, you can use propagated generics or have constants in a shared package to achieve what you want:
g_MMCM_RTL : if gGeneric_or_cConstant generate
mmcm_rtl : [entity library.]MMCME2_ADV
. . .
end generate g_MMCM_RTL;
g_MMCM_SIM : if not gGeneric_or_cConstant generate
mmcm_sim : [entity library.]MMCME2
. . .
end generate g_MMCM_SIM;