How do I find the error sequence in Finite State Machine?

Question

I'd like to verify the FSM correctness by verification in the verilog. for example, let we got the below FSM.

always @(*) begin
        win_n_st = win_c_st;
        case(win_c_st)
        IDLE : begin
                if(winapi_start)                
                win_n_st = VHSYNC_WAIT;
                else                                    
                win_n_st = IDLE;
        end
        VHSYNC_WAIT : begin
                if(v_anchor)            
                win_n_st = FIFO_WR;
                else                                    
                win_n_st = VHSYNC_WAIT;
        end
        FIFO_WR : begin
                if(winapi_start==0)             
                win_n_st = IDLE;
                else                                    
                win_n_st = FIFO_WR;
        end
        default :;
        endcase
end

you can see that FSM, there are 3 state. and first time wait winapi_start signal until 1 then go to next stat wait the v_anchor signal going to 1, then go to next state, wait until winapi_start is 0.

But what if we've got unexpected signal in FSM. then how do this FSM work? So I want to know is there any effectively way to verify the FSM? if yes, Would you let me know how do I verify the FSM? which kind of verify methodologies do we have?

Answer 1

You can verify correctness of your solution with test bench by providing different signals and checking the FSM / module response.

Test benches are cool!

You can read more here