I am writing a vhdl module that is to be implemented on the Artix-7 Basys 3 FPGA board. My design runs synthesis and implementation successfully however when I run write bitstream, I receive this error:
[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 29 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: segt[7].
As you can see, it lists segt as the problem port. This for the 7 segment display, I renamed it to "segt" from "seg" which is its default name but this did not keep the error from occurring. Its strange because I ran into this error when using the default name "sw" for the switches and "btnC" for the button in my module. I renamed "sw" to "sw1" and "btnC" to "btnC1" in the master.xdc file andIi stopped getting the error for those particular ports. Any help would be much appreciated.
Here is the main module:
entity timer_test is
port(
clk: in std_logic;
btnC1: in std_logic;
an: out std_logic_vector(3 downto 0);
segt: out std_logic_vector(7 downto 0);
led: out std_logic_vector(15 downto 0);
sw1: in std_logic_vector(15 downto 0)
);
end timer_test;
architecture arch of timer_test is
signal d3,d2, d1, d0: std_logic_vector(3 downto 0);
signal one_sec: std_logic;
begin
disp_unit: entity work.disp_hex_mux
port map(
clk=>clk, reset=>'0',
hex3=>d3, hex2=>d2, hex1=>d1, hex0=>d0,
dp_in=>"1101", an=>an, sseg=>segt);
divider_unit: entity work.clock_divider
port map(
clk=>clk,
start=>'1',
onesec=>one_sec);
counter_unit: entity work.count_down_timer
port map(
min_in(7 downto 0)=>sw1(15 downto 8),
sec_in(7 downto 0)=>sw1(7 downto 0),
clk=>clk,
one_sec=>one_sec,
reset=>btnC1,
d3=>d3 ,d2 =>d2, d1=>d1, d0=>d0,
led=>led);
end arch;
Relevant portion of the Master.xdc:
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw1[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw1[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw1[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw1[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw1[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw1[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw1[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw1[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw1[15]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
#7 segment display
set_property PACKAGE_PIN W7 [get_ports {segt[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[6]}]
set_property PACKAGE_PIN W6 [get_ports {segt[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[5]}]
set_property PACKAGE_PIN U8 [get_ports {segt[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[4]}]
set_property PACKAGE_PIN V8 [get_ports {segt[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[3]}]
set_property PACKAGE_PIN U5 [get_ports {segt[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[2]}]
set_property PACKAGE_PIN V5 [get_ports {segt[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[1]}]
set_property PACKAGE_PIN U7 [get_ports {segt[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[0]}]
set_property PACKAGE_PIN V7 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC1]
set_property IOSTANDARD LVCMOS33 [get_ports btnC1]
How can I fix these rule violations?
The error message specifically says that only 1 out of 29 ports is affected, so that tells us that we're just looking for one pin with an issue. The end of the error message specifies segt[7]. Your declaration for segt is the following:
segt: out std_logic_vector(7 downto 0);
Remember that in VHDL, downto is inclusive. That means segt has 8 elements.
Now look at your constraints file: there is no IO standard specified for segt[7]. You've only included segt[6] through segt[0], and none of those are included in your error. Just add segt[7]'s IO standard specification:
set_property PACKAGE_PIN <pin> [get_ports {segt[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[7]}]