Declaring a 2-D array in verilog gives me a error illegal redeclaration of the variable

Question

I am trying to initialize a 2d array in verilog as shown in the below code snippet.

parameter N=4;
 reg [N-1:0] number_c[2**N-1:0];
 reg [N-1:0] result_c;

after compiling I am getting the following error

ERROR:HDLCompilers:27 - "Combinational_output.v" line 24 Illegal redeclaration of 'number_c' ERROR:HDLCompilers:27 - "Combinational_output.v" line 25 Illegal redeclaration of 'result_c'

and my module looks like this

module Combinational_outputss(output number_c,output result_c
);

Answer 1

You are mixing ANSI and non-ANSI port styles. Refer to IEEE Std 1800-2012, section 23.2.3 Parameterized modules. This uses ANSI style:

module Combinational_outputss #(parameter N=4)
(
    output reg [N-1:0] number_c[2**N-1:0],
    output reg [N-1:0] result_c
);