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vhdlfpgacircuithdl

Preserving the widths of ports

I am trying to re-use netlists in other designs without the success.

I have a component which is translated to the netlist:

  entity c is
     port (...  sel : in std_logic_vector(31 downto 0); ... );

In the design I am using just sel(4 downto 0). The synthesis tools notices this behaviour and gives a warning:

'WARNING:Xst:647 - Input sel<31:5> is never used ..

I am generating netlist with properties:

  • keep hierarchy = true
  • add I/O buffers = off

Whenever I want to instantiate this netlist as an black-box module in other circuit I got an error:

ERROR:NgdBuild:76 - cannot be merged into block because one or more pins on the block, including pin "sel<31>", were not found in the file.

How can I preserve the size of sel? I should mention that the sel needs to be 32bits width since it's connected to the bus.

Solution

  • You could try driving the unused input ports to zero.