Output port missing in generated Verilog code from MyHDL

Question

I am trying to generate a verilog module from the following MyHDL module:

top.py:

from myhdl import *
from counter import Counter

def Top(clkIn, leds):
    counter = Counter(clkIn, leds)
    return counter

clkIn = Signal(bool(0))
leds = intbv(0)[8:0]

toVerilog(Top, clkIn, leds)

and,

counter.py:

from myhdl import *

def Counter(clk, count):
    c = Signal(modbv(0)[8:0])

    @always(clk.posedge)
    def logic():
        c.next = c + 1

    @always_comb
    def outputs():
        count.next = c

    return logic, outputs

However, in the generated file's module definition, (lines 1-3)

top.v:

module top (
    clkIn
);

input clkIn;
reg [7:0] counter_c;

always @(posedge clkIn) begin: TOP_COUNTER_LOGIC
    counter_c <= (counter_c + 1);
end

assign count = counter_c;

endmodule

leds[7:0] are missing. Even though these LEDs are unused I need them for my synthesizer to assign them to the proper pins on the development board. Why is MyHDL omitting them? and how can I make it include them?

Answer 1

Change leds = intbv(0)[8:0] into leds = Signal(intbv(0)[8:0]). Module (output) ports need to be declared as Signal.