VHDL: "others-like" command for std_logic signals

I would like to write a code in which my W_EN (std_logic) signal is set to one at need (if some conditions are met), and otherwise (if not differently specified) is zero. If W_EN would be a std_logic_vector I could do use the "others" statement in this way to do this (in the example code "W_EN" is called "one_if_one"):

signal cnt : unsigned (1 downto 0); --incremented at every clk_cycle
signal one_if_one : std_logic;

process (cnt)
begin
one_if_one <= (others => '0');
if (cnt = "01") then
 one_if_one <= '1';
end if;
end process;

But since W_EN is only a single bit, "others" can't be used with it. So I want to ask you if there is some way for implementing the command "set to zero if not differently specified in the process".

PS: I know I could simply write the else branch of the if, but I don't want to do this, since it would be more problematic with my real code.

PPS: the only solution I've found for the moment is to replace the line:

one_if_one <= (others => '0');

with

 one_if_one <= 'L';

but this would have a different meaning since the zero imposed by "others" is a strong one.

Thank you in advance for your help.

Solution

You don't need to do anything special here. If a signal is assigned multiple times within a particular process, the last assignment is the value that actually gets assigned.

process (cnt)
begin
  one_if_one <= '0';
  if (cnt = "01") then
    one_if_one <= '1';
  end if;
end process;

Is equivalent to

process (cnt)
begin
  if (cnt = "01") then
    one_if_one <= '1';
  else
    one_if_one <= '0';
  end if;
end process;

The others syntax that you have attempted to use is exclusively for assigning array types, so it has no meaning in relation to an object of type std_logic.