Let's say, i have two types of arrays:
type A_type is array (0 to 39) of std_logic_vector(7 downto 0);
type B_type is array (0 to 4) of std_logic_vector(63 downto 0);
And corresponding signals:
signal A : A_type := (others => (others => '0'));
signal B : B_type := ( x"0706050403020100",
x"0f0e0d0c0b0a0908",
x"1716151413121110",
x"1f1e1d1c1b1a1918",
x"2726252423222120");
And now, somewhere in the process i want bytewise cast A to B using two for loops, one wrapping another (1):
process(clk)
begin
if rising_edge(clk) then
for i in 1 to 5 loop
for j in 1 to 8 loop
A(i*j-1) <= B(i-1)(7+8*(j-1) downto 8*(j-1));
end loop;
end loop;
end if;
end process;
Of course, i could make it in a more straightforward manner (2):
for i in 0 to 4 loop
A(0+8*i) <= B(i)(7 downto 0);
A(1+8*i) <= B(i)(15 downto 8);
A(2+8*i) <= B(i)(23 downto 16);
A(3+8*i) <= B(i)(31 downto 24);
A(4+8*i) <= B(i)(39 downto 32);
A(5+8*i) <= B(i)(47 downto 40);
A(6+8*i) <= B(i)(55 downto 48);
A(7+8*i) <= B(i)(63 downto 56);
end loop;
As a result, i want to have byte array A, that stores vector array B in such way: proper_result, and expression (2) gives it. But expression (1) gives this: failed_result So the question is - am i missing something? Is it correct to multiply loop parameters (i*j), when acquiring array index?
p.s. i'm running xilinx vivado simulator with default sim options.
Shouldn't this:
A(i*j-1) <= B(i-1)(7+8*(j-1) downto 8*(j-1));
be more like this:
A(8*(i-1)+j-1) <= B(i-1)(7+8*(j-1) downto 8*(j-1));