In one of the designs I compiled using Yosys I saw that we can have private wires (wires with private name). For example, $0_s0[127:0]. So, I have few questions about them:
why do we have private wires in Yosys (what scenarios)?
does it always get converted to a unique name. For example, when I dump the whole design (using write_verilog), does it give me identical name as when I dump just the module that contains that private wire?
why do we have private wires in Yosys (what scenarios)?
because we need a mechanism to create names for intermediate wires. In an expression like assign x = (a+b)+c; there will be a wire holding the result of (a+b), and that wire will need a name.
Better to do it right and create a namespace for such names and separate them from user defined names. So later passes in the synthesis flow will always know which names to preserve and which names it can throw away.
does it always get converted to a unique name. For example, when I dump the whole design (using write_verilog), does it give me identical name as when I dump just the module that contains that private wire?
No.
Use a command like rename -enumerate to actually give public names to that wires if you care about this kind of consistency between different output files.