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cpucpu-architecturecpu-cache

Dirty bit value after changing data to original state


If the value in some part of cache is 4 and we change it to 5, that sets the dirty bit for that data to 1. But what about, if we set the value back to 4, will dirty bit still stay 1 or change back to 0?

I am interested in this, because this would mean a higher level optimization of the computer system when dealing with read-write operations between main memory and cache.


Solution

  • In order for a cache to work like you said, it would need to reserve half of its data space to store the old values.
    Since cache are expensive exactly because they have an high cost per bit, and considering that:

    • That mechanism would only detect a two levels writing history: A -> B -> A and not any deeper (like A -> B -> C -> A).
    • Writing would imply the copy of the current values in the old values.
    • The minimum amount of taggable data in a cache is the line and the whole line need to be changed back to its original value. Considering that a line has a size in the order of 64 Bytes, that's very unlikely to happen.
    • An hierarchical structure of the caches (L1, L2, L3, ...) its there exactly to mitigate the problem of eviction.

    The solution you proposed has little benefits compared to the cons and thus is not implemented.