I have a project with the following 3 files, and I am getting this error in the CA file:
Line 65: Type error near state_int ; current type std_logic_vector; expected type std_logic ERROR:HDLCompiler:854 - "" Line 40: Unit ignored due to previous errors.
CA FILE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CA is
port(clk,rst:in std_logic;
state:out std_logic_vector(0 to 8)
);
end CA;
architecture Behavioral of CA is
Component cell
port(L,R,clk,rst:in std_logic;
state:out std_logic
);
end component;
Component cellm
port(L,R,clk,rst:in std_logic;
state:out std_logic
);
end component;
signal state_int:std_logic_vector(0 to 8);
begin
state <= state_int;
U_cell0:cell
port map(clk => clk,
rst =>rst,
L => '0',
R => state_int,
state => state_int(0)
);
end Behavioral;
CELL FILE
entity cell is
port(L,R,clk,rst:in std_logic;
state:out std_logic
);
end cell;
architecture Behavioral of cell is
signal state_pr,state_nx:std_logic;
begin
state_nx <= ((not L) and R and state_pr) or (L and (not R));
Process(clk,rst)
Begin
if rst = '0' then
state_pr <= '0';
elsif rising_edge(clk) then
state_pr <= state_nx;
end if;
end process;
end Behavioral;
CELLM FILE
entity cellm is
port(L,R,clk,rst:in std_logic;
state:out std_logic
);
end cellm;
architecture Behavioral of cellm is
signal state_pr,state_nx:std_logic;
begin
state_nx <= ((not L) and R and state_pr) or (L and (not R));
Process(clk,rst)
Begin
if rst = '0' then
state_pr <= '1';
elsif rising_edge(clk) then
state_pr <= state_nx;
end if;
end process;
end Behavioral;
What am I doing wrong?
Actually you have three problems in your design. The first two problems were mentioned in the comments: