Chisel testing error in sodor/ rocket core ALU

Question

I am trying to customize and use the ALU source file of Sodor processor/Rocket core in a different project using chisel3. Running sbt test gives me the following error.

[info] - should carry out proper arithmatic and logical operations (with verilator) *** FAILED ***

[info]   chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@7): Missing IO() wrapper

[info]   at chisel3.core.Binding$.checkSynthesizable(Binding.scala:185)

[info]   at chisel3.core.Bits.do_apply(Bits.scala:97)

[info]   at chisel3.core.Bits.do_apply(Bits.scala:109)

[info]   at RiscvIoT.ALU$.isSub(alu.scala:44)

[info]   at RiscvIoT.ALU.<init>(alu.scala:68)

[info]   at RiscvIoT.ALUTester$$anonfun$2$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(aluTest.scala:41)

[info]   at RiscvIoT.ALUTester$$anonfun$2$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(aluTest.scala:41)

[info]   at chisel3.core.Module$.do_apply(Module.scala:29)

[info]   at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:191)

[info]   at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:191)

Following the guide on chisel 3 wiki on testing and debugging I believe that the initial error is at the line 44 (isSub function definition). But I can't figure out the problem and nothing I did solves the problem. I am posting my complete source file below for convenience.

import chisel3._
import chisel3.util._
import Common._

object ALU
{
  val SZ_ALU_FN = 4
  val ALU_X    = Bits(0)
  val ALU_ADD  = Bits(0)
  val ALU_SLL  = Bits(1)
  val ALU_XOR  = Bits(4)
  val ALU_OR   = Bits(6)
  val ALU_AND  = Bits(7)
  val ALU_SRL  = Bits(5)
  val ALU_SUB  = Bits(10)
  val ALU_SRA  = Bits(11)
  val ALU_SLT  = Bits(12)
  val ALU_SLTU = Bits(14)
  val ALU_COPY1= Bits(8)   

  def isMulFN(fn: Bits, cmp: Bits) = fn(1,0) === cmp(1,0)
  def isSub(cmd: Bits) = cmd(3)
  def isSLTU(cmd: Bits) = cmd(0)
}
import ALU._

class ALUIO extends Bundle {
  val xprlen = 32
  val fn = Bits(INPUT, SZ_ALU_FN)
  val in2 = UInt(INPUT, xprlen)
  val in1 = UInt(INPUT, xprlen)
  val out = UInt(OUTPUT, xprlen)
  val adder_out = UInt(OUTPUT, xprlen)
}

class ALU extends Module
{
  val io = new ALUIO
  val xprlen = 32
  val msb = xprlen-1

  // ADD, SUB
  val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)

  // SLT, SLTU
  val less  = Mux(io.in1(msb) === io.in2(msb), sum(msb),
              Mux(isSLTU(io.fn), io.in2(msb), io.in1(msb)))

  // SLL, SRL, SRA
  val shamt = io.in2(4,0).toUInt
  val shin_r = io.in1(31,0)
  val shin = Mux(io.fn === ALU_SRL  || io.fn === ALU_SRA, shin_r, Reverse(shin_r))
  val shout_r = (Cat(isSub(io.fn) & shin(msb), shin).toSInt >> shamt)(msb,0)
  val shout_l = Reverse(shout_r)

  val bitwise_logic =
    Mux(io.fn === ALU_AND, io.in1 & io.in2,
    Mux(io.fn === ALU_OR,  io.in1 | io.in2,
    Mux(io.fn === ALU_XOR, io.in1 ^ io.in2,
                       io.in1))) // ALU_COPY1

//  val out64 =
  val out_xpr_length =
    Mux(io.fn === ALU_ADD || io.fn === ALU_SUB,  sum,
    Mux(io.fn === ALU_SLT || io.fn === ALU_SLTU, less,
    Mux(io.fn === ALU_SRL || io.fn === ALU_SRA,  shout_r,
    Mux(io.fn === ALU_SLL,                       shout_l,
    bitwise_logic))))

  io.out := out_xpr_length(31,0).toUInt
  io.adder_out := sum
}

Answer 1

The exception thrown: chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@7): Missing IO() wrapper is due to the fact that in chisel3, io must be wrapped in IO(...)

It is perhaps a little hidden in the documentation (see https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2#deprecated-usage)

To fix, change the io declaration in ALU to:

val io = IO(new ALUIO)

You should also change the ALUIO to:

class ALUIO extends Bundle {
  val xprlen = 32
  val fn = Input(Bits(SZ_ALU_FN.W))
  val in2 = Input(UInt(xprlen.W))
  val in1 = Input(UInt(xprlen.W))
  val out = Output(UInt(xprlen.W))
  val adder_out = Output(UInt(xprlen.W))
}

Although I believe the old way is deprecated rather than an error.