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Why does yosys renumber vector ports?

My top level verilog module declares signals for the four LEDs on the myStorm ice40 board, which are labelled "LED1-LED4".

module top (
  output [4:1] LED
);
assign LED = 4'b1010;
endmodule

I use the same numbering in the .pcf file:

set_io LED[1] 37
set_io LED[2] 38
set_io LED[3] 39
set_io LED[4] 41

But in the .blif output, yosys has renumbered the signals:

.model top
.inputs
.outputs LED[0] LED[1] LED[2] LED[3]
...

so arachne-pnr complains:

top.pcf:4: fatal error: no port `LED[4]' in top-level module `top'

Does yosys expect that top level vector ports are always numbered from zero?

Solution

  • The reason for this is that the Yosys BLIF back-end was not using the hints for start offset and direction (upto/downto) stored in a Yosys Wire object for generating the single-bit net names.

    This is now fixed in commit 5c2c78e2dd. Thanks for bringing this to my attention.

    Update to latest git head of Yosys and you should get the results that you are expecting.