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system-verilogsystem-verilog-assertions

Would there be an issue, for system verilog functional coverage bins with similar sequences?


covergroup xxxx ;
 yyyy : coverpoint (zzzz)
{
bins sequence_1 = {0=>1=>2=>3};
bins sequence_2 = {0=>1=>2=>3=>4};
bins sequence_3 = {0=>1=>2=>3=>4=>5=>6=>7=>8=>9};
bins sequence_4 = {0=>1=>2=>3=>4=>5=>6=>7=>8=>9=>10=>11=>12=>13=>14=>15=>16=>17};
bins sequence_5 = {0=>1=>2=>3=>4=>5=>6=>7=>8=>9=>10=>11=>12=>13=>14=>15=>16=>17=>18};
bins sequence_6 = {0=>1=>2=>3=>4=>5=>6=>7=>8=>9=>10=>11=>12=>13=>14=>15=>16=>17=>18=>19};

}
 endgroup 
  • zzzz is a counter register which counts from 0 up to 3,4,9,17,18 or 19 depending on its input
  • In coding this functional coverage, the idea is to hit either one of the bins if a specific series of transitions occur, only one bin.

  • so if the transitions for example goes from 0 to 4 like in sequence_2, would that also hit sequence_1, since the 0 to 3 sequence is present in sequence_1

Thanks


Solution

  • Yes, if sequence_2 is hit, that implies that sequence_1 is also hit. What you really want is to cover what happens when the counter reaches its limit. i.e. does it go back to 0 or does it stay at the limit in the next cycle? There is no need to elaborate every intermediate value of the counter - a covergroup is not a checker. It is only recording that a certain scenario in your test was achieved.