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vhdl

Error in truth table in vhdl

Truth table

My code

I calculated Karnaugh map but my code is not correct. I am getting error: "Error for D='1' C='0' B='1' A='0'expected O='1', recieved O='0'".

Where I am making mistake?

library IEEE;
use IEEE.std_logic_1164.all;
entity truth_table is port(   A,B,C,D : in    std_logic;
                              O       : out   std_logic);
end truth_table;  

architecture behavior of truth_table isbegin

O <= (((not A) and C and D) or ((not D) and B and C) or (A and (not C) and D) or (A and C and (not B)));
end behavior;
Solution

  • The logical equation on the right of your signal 'O' is wrong it should be:

    O <= (((not D) and B and A) or ((not A) and C and B) or (D and (not B) and A) or (D and B and (not C)));

    See http://www.32x8.com/var4.html and try it yourself but note that the ordering of the columns is the opposite than in your truth table.