Do any of you know about a good VHDL coding style guide and good practises guide? With sw there are a lot of material, but with VHDL I don't see a reference example. I supposed because each maker has its own synthesis tool, and the code interpretation changes.
I'm looking for a short guide instead of a large book.
Thanks!
In general, a quick reference guide that I use fairly often is
http://allaboutfpga.com/category/vhdl/ The examples there have really good syntax and comments, it's mostly optimized VHDL and more geared towards learning it, so that may or may not be helpful.
If you are using Xilinx tools, they have templates included for just about every kind of operation or situation you could find yourself in. I would suggest familiarizing yourself with those if you want to avoid books like Reuse Methodology (https://www.amazon.com/Reuse-Methodology-Manual-System-Designs/dp/1402071418/ref=dp_ob_title_bk) or the designers guide for VHDL.
Other rules of thumb that are generally just understood are things like using std_logic's on the ports, tabulating for readability, registering outputs, and modularizing as much as possible.