vhdl
Truth Table in VHDL
I have to program the behavior of an entity:
library IEEE;
use IEEE.std_logic_1164.all;
entity truth_table is
port( A,B,C,D : in std_logic;
O : out std_logic);
end truth_table;
This entity is declared in the file with this code:
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of truth_table is
begin
end behavior;
and has the following properties:
• Inputs: A, B, C, D with type std logic
• Outputs: O with type std logic
The first (code) entity shall behave according to the following truth table:
Prior simplification with an optimization algorithm like Karnaugh Veith (KV diagram) is encouraged.
What I have done?
Am I going in right direction?
Solution
It would be better to post your code as code instead of an image. Even as an image, I can see that you have got:
0 <= A AND B AND C AND D; -- your output is O, not 0
You have repeated the same assignment twice for some reason.
The boolean equation does not match the truth table.
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