Best and Fastest Way for adding two std_logic_vector in VHDL

Question

In VHDL if I have a STD_LOGIC_VECTOR as per following declaration:

signal RAM_ADDR : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');

If I try to increment this address in a loop with the '+' operator as per following:

for i in 0 to 7 loop
   RAM_RW <= '1';
   wait until KEY_NUM'event;                    
   RAM_RW <= '0';
   RAM_ADDR <= RAM_ADDR + "1";
end loop;

I face the following error:

Error (10327): VHDL error at X.vhd(40): can't determine definition of operator ""+"" -- found 0 possible definitions

Can you suggest the best and fastes way to solve it (maybe without using a different type of data like integer)?

Up to now I am using the following (bad) solution:

case RAM_ADDR is
  when "000" =>
    RAM_ADDR <= "001";
  when "001" =>
    RAM_ADDR <= "010";
  when "010" =>
    RAM_ADDR <= "011";
  when "011" =>
    RAM_ADDR <= "100";
  when "100" =>
    RAM_ADDR <= "101";
  when "101" =>
    RAM_ADDR <= "110";
  when "110" =>
    RAM_ADDR <= "111";
  when "111" =>
    RAM_ADDR <= "000";
  when others =>
    RAM_ADDR <= "000";
end case;

Thanks in advance,

Answer 1

The most frequently recommended way to do this is to use the numeric_std package, and instantiate a signal of type unsigned.

use ieee.numeric_std.all;

...

signal RAM_ADDR : unsigned (2 downto 0) := (others => '0');

...

RAM_ADDR <= RAM_ADDR + 1;

You can try other methods that involve fighting the type system, but if you get used to using appropriate types early on, you can save yourself from certain kinds of bug in the future. In my opinion, using appropriate types can also lead to more readable code.