I have this simple VHDL Code aufg4.vhd
:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aufg4 is
Port (
clock : in std_logic
);
end aufg4;
architecture Behavioral of aufg4 is
signal tut_counter : integer range 0 to 90 := 0; -- counts tutorial time
begin
do_process :process(clock)
begin
if(rising_edge(clock)) then
report "tut_counter " & integer'image(tut_counter);
if(tut_counter >= 90) then
tut_counter <= 0;
report "tut_counter reset";
end if;
tut_counter <= tut_counter + 1;
end if;
end process;
end Behavioral;
And the testbench aufg4_tb.vhd
:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY aufg4_tb IS
END aufg4_tb;
ARCHITECTURE behavior OF aufg4_tb IS
COMPONENT aufg4
PORT(
clock : IN std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: aufg4 PORT MAP (
clock => clock
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
END;
When I simulate the Behavioral Model report
outputs:
...
at 885 ns(1): Note: tut_counter 88 (/aufg4_tb/uut/).
at 895 ns(1): Note: tut_counter 89 (/aufg4_tb/uut/).
at 905 ns(1): Note: tut_counter 90 (/aufg4_tb/uut/).
at 905 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 915 ns(1): Note: tut_counter 91 (/aufg4_tb/uut/).
at 915 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 925 ns(1): Note: tut_counter 92 (/aufg4_tb/uut/).
at 925 ns(1): Note: tut_counter reset (/aufg4_tb/uut/).
at 935 ns(1): Note: tut_counter 93 (/aufg4_tb/uut/).
...
So the if
-statement works properly, but the reassignment of the signal tut_counter
does not work.
So why is that?
And why does the simulation do not through an error because tut_counter
just has a range from 0 to 90
?
Using a else
instead solves the problem quite well!
do_process :process(clock)
begin
if(rising_edge(clock)) then
report "tut_counter " & integer'image(tut_counter);
if(tut_counter >= 90) then
tut_counter := 0;
report "tut_counter reset";
else
tut_counter := tut_counter + 1;
end if;
end if;
end process;
Otherwise you could use a variable: variable tut_counter : integer range 0 to 90 := 0; -- counts tutorial time