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system-verilogassertionsassertionsystem-verilog-assertions

how to alias signals from a nested interface in system verilog?

I have a nested interface, something like the pseudo example

interface a();
 logic a;
endinterface: a

interface B();
  logic b;
  a A();
  alias b = A.a; // THIS throws an error
endinterface: b

I want to write assertions on interface a from interface B

But it does not allow me to alias the signal. What are other alternatives?

Any suggestions?

Solution

  • Variables and hierarchical references cannot be used in alias statements.

    Your alternatives are:

    • Use assign b = A.a; instead of alias
    • Just use A.a in your assertion
    • Declare b using the let construct let b = A.a;

    I suggest using the let statement.