VHDL ATTRIBUTE keep

I am currently studying VHDL about SR Latch, and there comes to a part which I don't understand.

Can anyone explain What does ATTRIBUTE keep: boolean mean and what does it do in VHDL?

Thank you.

Solution

It is a user defined attribute, thus not part of the VHDL standard itself. It is typically used to instruct the synthesis tool that it should keep a certain signal, for example being a flip-flop, even through the synthesis tool may determine that the signal can be removed during optimization.

For Altera Quartus synthesis tool, see this description: keep VHDL Synthesis Attribute

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