I'm building a VGA output block that is using nested elements that provide similar interfaces to build up the picture. The configuration then determines the actual screen layout.
So far, I've created one configuration for each block, but I'd really like to use a single, nested configuration. It is allowed in the BNF, and I've found example code that uses this, but I cannot get my code to compile.
Inside work there are
entity everything is
...
end entity;
architecture syn of everything is
...
begin
gfx : vga;
end architecture;
component source is
...
end component;
entity vga is
...
end entity;
architecture syn of vga is
...
begin
src : source;
end architecture;
entity testpattern is
...
end entity;
architecture syn of testpattern is
...
end entity;
Now I'd like to put all of this together using a configuration:
configuration conf of everything is
for syn
for gfx : vga
use entity work.vga(syn);
for syn -- Error reported here
for src : source
use entity work.testpattern(syn);
end for;
end for;
end for;
end for;
end configuration;
I get an error message from Quartus
Error (10392): VHDL Block Specification error at everything.vhd(106): cannot find "syn"
The BNF says that an unqualified (architecture) name is expected at this point. What is missing here?
A few modifications (additions, and moving your component declaration to an architecture declarative part):
entity source is
end entity;
architecture foo of source is
begin
end architecture;
entity vga is
end entity;
architecture syn of vga is
component source is
end component;
begin
src : source;
end architecture;
entity everything is
end entity;
architecture syn of everything is
component vga is
end component;
begin
gfx : vga;
end architecture;
entity testpattern is
end entity;
architecture syn of testpattern is
begin
end architecture;
configuration conf of everything is
for syn
for gfx : vga
use entity work.vga(syn);
for syn -- Error reported here
for src : source
use entity work.testpattern(syn);
end for;
end for;
end for;
end for;
end configuration;
And your code analyzes, elaborates and simulates (while doing perfectly nothing).
%% ghdl -a richter.vhdl
%% ghdl -e conf
%% ghdl -r conf
%%
An added entity and architecture for source. A component declaration for vga. Move the component declaration for source to architecture syn of vga. Get rid of all the annoying "..."s.
You'll likely need a configuration for testpattern that uses the configuration conf of everything to get you testbench (if testpattern is a testbench) to elaborate and run. It's a bit premature to show that here.
Addendum
After seeing you answer a VHDL question today I took another look at this question and your comment:
Hm, I have the component definition living in a package, because I need that in multiple places. The largest difference otherwise would be the entity source and the unused architecture for it -- do I always need to define an entity with the same name as a component, even if I'm not going to use it? – Simon Richter Oct 26 '16 at 2:05
I modified the above code with component declarations in a package for vga and source, deleted the entity and architecture for source:
package components_pkg is
component vga is
end component;
component source is
end component;
end package;
---------------------------------------
use work.components_pkg.all;
entity vga is
end entity;
architecture syn of vga is
begin
src : source;
end architecture;
---------------------------------------
use work.components_pkg.all;
entity everything is
end entity;
architecture syn of everything is
begin
gfx : vga;
end architecture;
---------------------------------------
entity testpattern is
end entity;
architecture syn of testpattern is
begin
end architecture;
---------------------------------------
configuration conf of everything is
for syn
for gfx : vga
use entity work.vga(syn);
for syn -- Error reported here
for src : source
use entity work.testpattern(syn);
end for;
end for;
end for;
end for;
end configuration;
This also analyzes, elaborates and runs (while doing nothing).
This demonstrates that component declarations can be used in place of entity declarations visible in resource library work,
Also demonstrates component declarations not used are ignored (made visible by use clause).
That you still received error ID: 10392 implies that the architecture synfor testpattern weren't both analyzed at the type the configuration declaration conf was elaborated.
With an emptied working library another VHDL tools gives a similar message if the syn architecture is commented out -
ghdl -e conf
/usr/local/bin/ghdl1-llvm: cannot find architecture "syn" of entity "testpattern"
What this boils down to is there wasn't an architecture syn found in library work for entity testpattern when configuration conf was elaborated and elaboration failed.
You could notice the design units are shown above (separated by "----...") in analysis order.