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Yosys FSM Detection State Assignments?

I am attempting to use Yosys for a project of mine, but I am confused about the FSM detection.

I read this post: FSM export using Yosys

My question is about the state transitions detected from the Verilog file by Yosys. On the post that the link above points to, I don't see any way to transition from state 1 to state 3; however, in the generated graph there is. How is this? Thanks in advance.

Solution

  • The state names are arbitrarily assigned. They do not encode the numeric value of the state register that corresponds to the state. Looking at the diagram and the original Verilog code, I'd say the mapping is as follows for that example:

    s0: state == 0
s1: state == 2
s2: state == 1
s3: state == 3