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VHDL frequency divider code

I have this code:

architecture Behavioral of BlockName is
  signal t: std_logic;
  signal c : std_logic_vector (1 downto 0);
begin
  process (reset, clk) begin
    if (reset = '1') then
      t <= '0';
      c <= (others=>'0');
    elsif clk'event and clk='l' then
      if (c = din) then
        t <= NOT(t);
        c <= (others=>'0');
      else
        c <= c + 1;
      end if;
    end if;
  end process;
  dout <= t;
end Behavioral;

This code's role is to divide the frequency when it gets input (clock + value) and outputs a divided frequency.

Now my questions:

  1. What does this c <= (others=>'0'); mean ?
  2. What value does t get here t <= NOT(t); ? the last t value? does the <= work as = ?
Solution
    1. c <= (others=>'0'); is equivalent to c <= "00";
    2. t <= not(t); assigns to t the opposite of the current value in t.
    3. = is an equality comparison in VHDL.
    4. <= is signal assignment in VHDL.