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Use a type before it's declared in VHDL (2008)

Is it possible in any version of VHDL, maybe in 2008, to use a type before it's declared?

E.g. I have this array declaration in the architecture of an entity:

type my_array is array (integer range <>) of my_type;

And still in the same architecture section, but later in the file I have this:

type my_type is record 
    my_field: signed(31 downto 0);
end record;

Now this gives the following error in Vivado:

[Synth 8-1031] my_type is not declared

The solution is of course to move the record declaration above the array declaration. However this gets very complicated and messy with the number of types increasing (since you basically have to topologically sort your types taking their dependencies into account).

Something like this is supported in every major programming language so I figured maybe it would also exist in VHDL. I also vaguely remember reading about this having been added to VHDL 2008 but can't find any resources about it and my quick test with VHDL 2008 was negative.

So is it possible to use a type in VHDL before its declared, given that the type is declared still in the same architecture, same file, but a few lines below?

Solution

  • Is it possible in any version of VHDL, maybe in 2008, to use a type before it's declared?

    No.

    IEEE Std 1076-2008 6. Declarations

    6.1 General

    The language defines several kinds of named entities that are declared explicitly or implicitly by declarations. Each entity’s name is defined by the declaration, either as an identifier or as an operator symbol or a character literal.
    ...
    For each form of declaration, the language rules define a certain region of text called the scope of the declaration (see 12.2). ...

    12.2 Scope of declarations

    The scope of a declaration, except for an architecture body, extends from the beginning of the declaration to the end of the immediately closing declarative region; the scope of an architecture body extends from the beginning to the end of the architecture body. In either case, this part of the scope of a declaration is called the immediate scope.

    12.3 Visibility

    A declaration is visible only within a certain part of its scope; this part starts at the end of the declaration except in the declaration of a design unit other than a PSL verification unit, a package declaration, or a protected type declaration, in which case it starts immediately after the reserved word is occurring after the identifier of the design unit, a package declaration, or protected type declaration. This rule applies to both explicit and implicit declarations.

    It's the visibility rules stopping you from referencing a type before it's declared.

    Also VHDL does not support forward declaration of types other than interface type declarations (generic types), but does for subtypes as your example my_array shows.

    The generic types Brian indicates usefulness is limited lacking synthesis vendor support as well as limitations on operations of a type (see 6.5.3 Interface type declarations) summarized in Peter Ashenden's book VHDL 2008 Just the New Stuff:

    1.1 Generic Types

    VHDL-2008 defines a number of rules covering formal generic types and the ways they can be used. The formal generic type name can potentially represent any constrained type, except a file type or a protected type. The entity can only assume that operations available for all such types are applicable, namely: assignment; allocation using new; type qualification and type conversion; and equality and inequality operations. The formal generic type cannot be used as the type of a file element or an attribute. Moreover, it can only be used as the type of an explicitly declared constant or a signal (including a port) if the actual type is not an access type and does not contain a subelement of an access type. For signals, the predefined equality operator of the actual type is used for driver update and event detection.