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vhdl

How to change to when statement

can someone help me on how to change this vhdl code to using 'when' statement?

Here is the code that I have written:

library IEEE;
use IEEE.std_logic_1164.all;

entity sel2_1 is
   port( A, B, SEL : in std_logic;
         outsgnl    : out std_logic);
end sel2_1;

architecture EX1 of sel2_1 is
begin
   outsgnl <= (not SEL and A) or (SEL and B);
end EX1;

the simulation result is as follows: simulation

Solution

  • When keyword is used in different VHDL assignments. Assuming SEL is only '0' or '1' you can simpley replace 

    outsgnl <= (not SEL and A) or (SEL and B);

    by a selected signal assignment, often referred as with/select assignment 

    with SEL select outsgnl <=
    A when '0',
    B when others;

    Alternatively you may use conditional signal assignment often referred as when/else

    outsgnl <= A when SEL = '0' else B;