Long story short, a colleague of mine, in charge of the hardware is struggling with the optimization of his VHDL code for his FPGA. I, being much more on the software-side of things, was wondering if there would be something similar to the keyword "volatile" in VHDL (like, for example, in C++).
The idea would be to avoid the compiler to optimize "too much" the code, providing a broken firmware for the FPGA without touching the setting of the environment (in order for the code to be usable on a different design software).
Sorry in advance, if it is a silly question, it was just out of curiosity for me, and maybe the beginning of a solution for my colleague.
Thanks.
No, "volatile" has no place in VHDL.
If he's sharing a variable (as opposed to a signal) between processes, make it a "protected object" (VHDL-2002,2008).
If he's finding synthesis is deleting parts of the design, then they are redundant and cannot affect the result. The problem then is not optimisation, but incorrect VHDL in the first place, which should be better tested in simulation before getting to synthesis.
If he has a specific reason to preserve a named object (signal, etc) through the synthesis process where it is a duplicate of some other signal, then he can attach "keep" or "dont_touch" attributes to it - the exact syntax varies between synthesis tools.