I've already done searches here and found some insight, but some of the concepts about using this kind of loop elude me. Here are my modules for the Half-Adder and Full-Adder:
module HalfAdder( A, B, Cout, S );
input A, B;
output Cout, S;
assign Cout = A & B;
assign S = A ^ B;
endmodule
module FullAdder(FA_A, FA_B, Cin, FA_S, Cout);
input FA_A, FA_B, Cin;
output FA_S, Cout;
wire ha0_S, ha0_C, ha1_C;
HalfAdder ha0( .A( FA_A ),
.B( FA_B ),
.Cout(ha0_C ),
.S( ha0_S )
);
HalfAdder ha1( .A( Cin ),
.B( ha0_S ),
.Cout(ha1_C ),
.S( FA_S )
);
assign Cout = ha0_C | ha1_C;
endmodule
And here is my RCA code:
module RCA8(A_8, B_8, Cin, Cout, S_8);
input [7:0] A_8, B_8;
input Cin;
output Cout;
output [7:0] S_8;
wire [8:0] c;
assign c[0] = Cin;
genvar i;
generate
for (i = 0; i < 8; i=i+1)
begin : make_fadders
FullAdder fa( .FA_A( A_8[i] ),
.FA_B( B_8[i] ),
.Cin( c[i] ),
.FA_S( S_8[i] ),
.Cout( c[i+1] )
);
end
endgenerate
assign Cout = c[8];
endmodule
I'm trying to get the simulator (iSim) to run. When I do check syntax it works, but when I try to generate a programming file it fails and when I run Mapping it returns a bunch of warnings. The iSim says error 861: failed to link the design. Doesn't Mapping have to do with that?
One thing I don't really understand is that in the implementation and/or simulation view, it only shows one fullAdder module in the RCA's drop down tree. Should it show 8? Or is that not how this works?
I really want to make this work, because the alternative is making 8 fadders by hand (as the assignment shows...) as opposed to learning how to use this useful tool.
Other details: Windows 10, using 32-bit Project Navigator Xilinx 14.7
Thanks for any help!
Check out this link. Renaming a file called collect2.exe may resolve your issue.