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vhdlmodelsimdigital-logic

Why does this VHDL code work? 4:2 Priority encoder using Case statement

The code is below:

entity encoder_case is
 port(
     din : in STD_LOGIC_VECTOR(3 downto 0);
     dout : out STD_LOGIC_VECTOR(1 downto 0)
     );
end encoder_case;

architecture encoder_case_arc of encoder_case is
begin
encoder : process (din) is
begin
    case din is
        when "1000" => dout <= "00";
        when "0100" => dout <= "01";
        when "0010" => dout <= "10";
        when "0001" => dout <= "11";
        when others => dout <= "ZZ";
    end case;
end process encoder;
end encoder_case_arc;

Now you'd expect that this code does not cover cases suh as when din is "0101", "1010" etc. But for those inputs, dout produces "10" and "11" respectively. Why does this work? Does VHDL intelligently give higher priority to the higher order bits? Does it 'know' that we're trying to accomplish a priority encoder here?

Solution

  • All cases under "others" should produce "ZZ", except if another signal would be driving dout. We will indeed need your testbench and waveforms to clarify this.

    As for your other questions: There is no such thing as priority in a case, not in terms of the order of options and certainly not in the sense of higher/lower bits.

    And it certainly does not "know" what you want to do. What you get is what you wrote, as always ... It might just take some time to understand what you exactly wrote sometimes.