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system-verilogmodelsim

Viewing SV testbench tasks,signal names in Modelsim

I want to view in Modelsim SV driver signals, tasks to debug. I don't want to add display statements everywhere to know how my test is progressing.Please let me know if there is a way we can do it. I tried adding the signals from simulation but when I restart the simulation the tool hangs

Solution

  • $display and (for UVM) uvm_info statements are the most common ways of debugging signals that reside inside functions and tasks. ModelSim/Questa have the ability to add signals from inside a uvm_component to a waveform, but not transient signals that exist only inside a function or task. One trick I do to view them inside the waveform or log is to create an observe signal outside the function/task that I assign the value that I want to observe whenever the task is called.