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arraysrangevhdl

Array of parametrized elements in VHDL

In VHDL it is possible to create array type of parametrizable range in the way:

type t_array_type is array (natural range <>) of std_logic_vector(7 downto 0)

Now, is it possible to create an array of parametrizable elements? I.e. to have an array type where, while instantiating a signal, it is possible to define a range of std_logic_vector? Purpose of that is not having to declare separate array types for every std_logic_vector range.

Solution

  • Ok, I found it. Declare type as:

    type t_array_type is array (natural range <>) of std_logic_vector;

    and then instantiate as:

    signal t_array_type(23 downto 0)(7 downto 0);