What are the conditions when a 2D memory instantiated in Verilog is mapped to BRAM by ISE?

Question

Upon searching in multiple forums, I did not find a comprehensive answer.

I would like to understand, when does [PARAM1:0] ram [PARAM2:0] inferred as a Block RAM by the ISE synthesizer and when it is not?

Answer 1

This list of conditions might be incomplete:

• Size
  If the memory is to small, ISE will use a distibuted RAM (LUT-RAM) instead of a BlockRAM. The size / area of your memory must be mapable to a single or group of BlockRAMs. A single BlockRAMs can have 8,9,16,18,32,36,64,72 bits per data port. Other sizes are possible if the number of memory lines matches.

• Ports
  BlockRAM supports:

  • single-port (SP),
  • simple-dual-port (SDP),
  • enhanced-simple-dual-port (ESDP) and
  • true-dual-port (TDP)

  memories. Combinations with one write port and n read ports a also possible.

• Reset
  BlockRAMs don't support resets. So if you memory can be reset, if can be inferred as BRAM.
• ClockEnable (CE), Write-Enable (WE), Byte-Write-Enable (BWE)
  BlockRAMs support CE and WE, but usually no BWE.
• Timing
  The memory must be synchronously written and either synchronously read or asynchronously read with from a registered address.
• Output Registers (OUT_REG)
  Output registers are optional, but improve the overall timing. The synthesizer might move the OUT_REG from logic into the BlockRAM, which has embedded output registers.

Our open-source library PoC contains 4 possible on-chip RAM implementations written in generic VHDL code, which can be mapped to Xilinx BlockRAMs. I assume you can read and understand these VHDL snippets, to translate it into Verilog code :). Alternatively, Xilinx offers a synthesis guide (UG 626, v14.4, p. 73)), which lists VHDL and Verilog design patterns of synthesizable code.