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VHDL 2008 > generic package in an entity: error expecting BASICID or EXTENDEDID

When trying to declare an entity with a formal generic package (ieee.fixed_generic_pkg):

library ieee;
context ieee.ieee_std_context;

entity myent is
  generic ( package myfpkg is new ieee.fixed_generic_pkg generic map (<>) );
end entity;

I get the following error:

Syntax error at or near "package", expecting BASICID or EXTENDEDID

I have also tried:

library ieee;
context ieee.ieee_std_context;
use ieee.fixed_generic_pkg;

entity myent is
  generic ( package myfpkg is new ieee.fixed_generic_pkg generic map (<>) );       
end entity;

that doesn't work neither.

However, if I declare any dummy instance of the package, it works without any error:

library ieee;
context ieee.ieee_std_context;
package fpkg is new ieee.fixed_generic_pkg;

--

library ieee;
context ieee.ieee_std_context;

entity myent is
  generic ( package myfpkg is new ieee.fixed_generic_pkg generic map (<>) );       
end entity;

What is the proper way of declaring an entity with a formal generic package, without having to previously instantiate a package of the same type?

EDIT

The tool I'm using is HDL Designer 2015.1b. I think that generic packages are supported. Indeed, the following example throws no error:

library slfnlib;
use slfnlib.gen_consts;
use slfnlib.gen_wb_ctypes;

package gen_ctypes is
  generic ( package cs is new slfnlib.gen_consts generic map (<>) );  

  package wb is new slfnlib.gen_wb_ctypes generic map (
    g_mo => cs.g_mo,
    g_bas => cs.g_bas );

end package;

EDIT2

While working with several generic packages (declarations, instantiations, use...), I realized that full projects are correctly compiled. I also got the same error several times, when analizing only parts of them.

Then, I concluded that I can not analyze any generic package/entity on its own with DesignChecker. However, there is an easy workaround, which is just to use those components as we would in any practical design. That should be done anyway, in order to either simulate and synthetize the design. The key message is not bother with what the tools provide, until the body of the code actually makes sense as a practical design.

Solution

  • You code looks to have a similar structure to the example in section 6.5.7.2 of the LRM ("Generic map aspects") except your top-level is an entity whereas in their example it is a package.

    Your original code compiled fine on the two tools I tried, so it looks to me like there is an issue in whatever tool you are using. I suggest you take it up with the tool vendor.