case sensitivity while using Verilog module in VHDL

Question

During mixing VDHL and Verilog I came across a problem with case sensitivity.

The parameter "APB_ADDR" is written in upper case and the wire "apb_addr" in lower case. Since Verilog is case sensitive it can differ between the two expressions.

module verilog_module #(
...
parameter APB_ADDR              = 32,
...
) (
...
input   wire    [APB_ADDR-1:0]  apb_addr,
input   wire                    apb_sel,
input   wire                    apb_enable,
input   wire                    apb_write
....
);

Now I want to instantiate the module in VDHL:

inst0: entity work.verilog_module 
GENERIC MAP (
    APB_ADDR => APB_ADDR_WIDTH
)
PORT MAP(
    ...
    apb_addr => apb_addr,
    ...
);

Synthesis fails. The generic "apb_addr" is not know. VHDL has no case sensitivity.

How can I access the generic APB_ADDR? I don't want to change the IP core written in Verilog.

Answer 1

If you are unable to change the IP core, another option is to create a wrapper (in Verilog) that instanciates the core, sets the APB_ADDR parameter, and passes apb_addr and the other signals between the core and your VHDL entity.