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vhdlflip-flop

Different flipflops - different outputs for one reset input


I have 9 flipflops and one reset input. I need to set outputs of 8 flipflops to 0 when reset is 0. And output of one flipflop to 1. This flipflop unique and never changed. How to do it?

Code of flipflops:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ff is
   port
   (
      clk : in std_logic;
      rst : in std_logic;     
      d : in std_logic;
      q : out std_logic
   );
end entity d_ff;

architecture logicFunc of d_ff is
begin
   process (clk) is
   begin
        if (rst='0') then   
            q <= '0';
        elsif (clk'event and clk = '1') then 
            q <= d; 
        end if;
   end process;
end architecture logicFunc;

Now this code sets all flipflops to 0 when reset is 0 and I can't change output of first flipflop in main program


Solution

  • The 8 flip-flops which reset to '0' you can use the code you presented. For the other flip-flop you can create another entity d_ff1:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    
    entity d_ff1 is
       port
       (
          clk : in std_logic;
          rst : in std_logic;     
          d : in std_logic;
          q : out std_logic
       );
    end entity d_ff1;
    
    architecture logicFunc of d_ff1 is
    begin
       process (clk) is
       begin
            if (rst='0') then   
                q <= '1';
            elsif (clk'event and clk = '1') then 
                q <= d; 
            end if;
       end process;
    end architecture logicFunc;
    

    This way is in keeping with the way you wanted to have a separate flip-flop entities.