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arraysvhdl

Selecting array in VHDL


I have a package which has an array.

    type reg_array_type is array (1 downto 0) of std_logic_vector(7 downto 0);   
    constant REG_ARRAY_C : reg_array_type := (
    x"00", 
    x"01";

I'm using this package in

data_write      <= REG_ARRAY_C(conv_integer(unsigned(index)));

What I'm trying to do is access the data from the package (x"00", x"01") individually and store it to data_write. In my simulation however only x"01" is being stored there.

How do I access x"00" from the array to store it first in data_write then store x"01"?


Solution

  • If you want to access the first byte then you just have to write...

    data_write      <= REG_ARRAY_C(1);  -- data_write is assigned x"00"
    

    ... And the second one :

    data_write      <= REG_ARRAY_C(0);  -- data_write is assigned x"01"
    

    If I can give you an advice, I prefer to use TO instead of DOWNTO when declaring an array since it is more understandable: the first byte is the 1, the last one is N like :

    type my_array is array (1 TO N) of std_logic_vector(7 downto 0);
    

    Of course that's just a suggestion