Below is the code of VHDL which uses IF block. In the last "elsif", the value of "my_choice" is assigned to "ch4". Then "else" block is executed, since no condition is satisfied. But, is there any chance that "my_choice" gets some other value other than (ch1,ch2,ch3,ch4), like high impedence (or anything else)? If so, how can i avoid that? Since this assignment can change the operation of the code.
entity entity_name
port
.....
.....
end entity_name;
architecture bhvr of entity_name
type choices is (ch1, ch2, ch3, ch4);
signal my_choice,next_choice : choices;
begin
process(clk, reset)
begin
if reset='1' tehn
--------reset
else
my_choice<=next_choice;
end if;
end process;
process(my_choice)
begin
if my_choice = ch1 then
next_choice <= ch2;
elsif my_choice = ch2 then
next_choice <= ch3;
elsif my_choice = ch3 then
next_choice <= ch4;
else ------------------------------------coming to ch4
---- task for ch4
end process;
end architecture;
Since my_choice is type choices, which is enumerated type with values 'ch1', 'ch2', 'ch3', 'ch4', then my_choice will always have one of these 4 values, at least in simulation.
In hardware, the available value space depends on the implementation, for example if the values are made as one-hot or binary. After start-up a reset is a good way to make sure that the value is well-defined to one of the 4 values, and if the circuit then adheres to the timing requirements, then the value will stay in the defined values space of the 4 values.