VHDL when-else error

Question

I'm new in VHDL and have simple errors. I'm trying to create MUX using when else construction. Errors are two types:

Error (10500): VHDL syntax error at lab13.vhd(21) near text "when"; expecting ";"

Error (10500): VHDL syntax error at lab13.vhd(21) near text "else"; expecting ":=", or "<="

And these errors are for every string with when else.

And here is the code:

entity lab13 is
port (SW : in  STD_LOGIC_VECTOR (17 downto 0);
LEDG : out STD_LOGIC_VECTOR (2 downto 0);
LEDR : out STD_LOGIC_VECTOR (17 downto 0));
end lab13;



architecture logicFunc of lab13 is
begin  
    process
variable a, b, c : STD_LOGIC_VECTOR (2 downto 0) :=0;
begin
    a(0) := SW(0) when (SW(15) = '0') else SW(3);
    b(0) := SW(6) when (SW(15) = '0') else SW(9);
    c(0) := a(0) when (SW(16) = '0') else b(0);
    LEDG(0) <= c(0) when (SW(17) = '0') else SW(12);

    a(1) := SW(1) when (SW(15) = '0') else SW(4);
    b(1) := SW(7) when (SW(15) = '0') else SW(10);
    c(1) := a(1) when (SW(16) = '0') else b(1);
    LEDG(1) <= c(1) when (SW(17) = '0') else SW(13);

    a(2) := SW(2) when (SW(15) = '0') else SW(5);
    b(2) := SW(8) when (SW(15) = '0') else SW(11);
    c(2) := a(2) when (SW(16) = '0') else b(2);
    LEDG(2) <= c(2) when (SW(17) = '0') else SW(14);
end process;
   LEDR <= SW;
end logicFunc;

So, how to solve these problems?

Answer 1

The when in sequential statement for conditional variable or signal assignment was introduced in VHDL-2008, which is not fully supported in Altera Quartus.

The implementation can instead be made with signals, and no process, like:

architecture logicFunc of lab13 is
  signal a, b, c : STD_LOGIC_VECTOR (2 downto 0);
begin

  a(0) <= SW(0) when (SW(15) = '0') else SW(3);
  b(0) <= SW(6) when (SW(15) = '0') else SW(9);
  c(0) <= a(0) when (SW(16) = '0') else b(0);
  LEDG(0) <= c(0) when (SW(17) = '0') else SW(12);

  a(1) <= SW(1) when (SW(15) = '0') else SW(4);
  b(1) <= SW(7) when (SW(15) = '0') else SW(10);
  c(1) <= a(1) when (SW(16) = '0') else b(1);
  LEDG(1) <= c(1) when (SW(17) = '0') else SW(13);

  a(2) <= SW(2) when (SW(15) = '0') else SW(5);
  b(2) <= SW(8) when (SW(15) = '0') else SW(11);
  c(2) <= a(2) when (SW(16) = '0') else b(2);
  LEDG(2) <= c(2) when (SW(17) = '0') else SW(14);

  LEDR <= SW;

end architecture;

The initialization value of a, b, and c is not required, and otherwise it must be made using:

variable a, b, c : std_logic_vector (2 downto 0) := (others => '0');

If something like when is handy before VHDL-2008, then a tern function can be written as:

function tern(cond : boolean; res_true, res_false : std_logic) return std_logic is
begin
  if cond then
    return res_true;
  else
    return res_false;
  end if;
end function;

And then used as:

a(0) := tern(SW(15) = '0', SW(0), SW(3));