Generic vector in VHDL, with position of assignment determined by variable

Question

I have a simple state machine written in VHDL. Size of every vector and variable is determined by a generic constant "n". The idea is: when I change "n", I want to immediately be able to synthesize. Part of the design is a vector in "1 of N" code.

Ports & signals definitions:

tester: out std_logic_vector(n-1 downto 0); -- port
signal I: integer range 0 to n-1:=0;  -- signal

What I have:

process(I)
begin
    if I=0 then
        tester<="0001";
        elsif I=1 then
        tester<="0010";
        elsif I=2 then
        tester<="0100";
        else
        tester<="1000";
    end if;
end process;

This obviously works only for n=4. What I want:

process(I)
begin
    tester<=(I=>'1', others=>'0');
end process;

This does not synthesize however, due to "choice is not constant" error. I is changed by one of the states and it can be changed in any pattern, hence the problem.

Answer 1

Instead you can do:

process(I)
begin
    tester    <= (others => '0');
    tester(I) <= '1';
end process;