I tried to create a simple hello world testbench for a two input AND
gate in Quartus. I am consistently running into the following error:
Error (10500): VHDL syntax error at Scott_2InputAndGate_Test.vhd(19) near text "IN"; expecting an identifier ("in" is a reserved keyword), or a string literal
My code:
--------------------------------------
------------TOP LEVEL ENTITY----------
--------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
ENTITY s_2InputAndGate IS
PORT(a, b : IN std_logic;
z : OUT std_logic);
END ENTITY s_2InputAndGate;
ARCHITECTURE behaviour OF s_2InputAndGate IS
BEGIN
z <= a AND b;
END ARCHITECTURE behaviour;
--------------------------------------
------------TESTBENCH-----------------
--------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
--No Entity for TestBench;
ENTITY s_2InputAndGate_Test IS END;
--Line 10
--Line 11
--Line 12...etc
--Behaviour of the Test bench;
ARCHITECTURE behaviour OF s_2InputAndGate_Test IS
SIGNAL A_test, B_test : IN std_logic; --lINE(19 - ERROR HERE!)
Z_test: OUT std_logic;
BEGIN
A_test <= 0;
B_test <= 0;
WAIT FOR 50ns;
A_test <= 0;
B_test <= 1;
WAIT FOR 50ns;
A_test <= 1;
B_test <= 0;
WAIT FOR 50ns;
A_test <= 1;
B_test <= 1;
WAIT;
END ARCHITECTURE behaviour;
The compiler seems to keep complaining about the signal declaration in the testbench. I have checked the syntax and can't seem to find any obvious problem with it. Anyone have any ideas why this line should prevent a successful compilation?
SIGNAL A_test, B_test : IN std_logic;
Signals do not have a direction. Just use:
SIGNAL A_test, B_test : std_logic;
Also, your line Z_test: OUT std_logic;
is not valid. You can add this signal declaration in with the other two once you remove the direction.