Testbench not working

Question

The following test bench fails to provide the intended signals for QAU and QBU :

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY VHDLfinal_vhd_tst IS
END VHDLfinal_vhd_tst;
ARCHITECTURE VHDLfinal_arch OF VHDLfinal_vhd_tst IS
-- constants  
CONSTANT clk_period : TIME := 20 ns;
CONSTANT num_clk_cycles : INTEGER := 100;  
CONSTANT n_period : TIME := 80 ns;
CONSTANT n_cycles : INTEGER := 50;                                               
-- signals                                                   
SIGNAL CLOCK_50 : STD_LOGIC := '0';
SIGNAL LOAD : STD_LOGIC;
SIGNAL Number : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL Q : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL QAU : STD_LOGIC;
SIGNAL QBU : STD_LOGIC;
SIGNAL Reset : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL TEST_A : STD_LOGIC;
SIGNAL TEST_Ap : STD_LOGIC;
SIGNAL TEST_B : STD_LOGIC;
SIGNAL TEST_Bp : STD_LOGIC;
SIGNAL TEST_Count : STD_LOGIC;
COMPONENT VHDLfinal
    PORT (
    CLOCK_50 : IN STD_LOGIC;
    LOAD : IN STD_LOGIC;
    Number : IN STD_LOGIC_VECTOR(0 TO 7);
    Q : OUT STD_LOGIC_VECTOR(0 TO 7);
    QAU : IN STD_LOGIC;
    QBU : IN STD_LOGIC;
    Reset : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    TEST_A : OUT STD_LOGIC;
    TEST_Ap : OUT STD_LOGIC;
    TEST_B : OUT STD_LOGIC;
    TEST_Bp : OUT STD_LOGIC;
    TEST_Count : OUT STD_LOGIC
    );
END COMPONENT;
BEGIN
    i1 : VHDLfinal
    PORT MAP (
-- list connections between master ports and signals
    CLOCK_50 => CLOCK_50,
    LOAD => LOAD,
    Number => Number,
    Q => Q,
    QAU => QAU,
    QBU => QBU,
    Reset => Reset,
    TEST_A => TEST_A,
    TEST_Ap => TEST_Ap,
    TEST_B => TEST_B,
    TEST_Bp => TEST_Bp,
    TEST_Count => TEST_Count
    );
init1 : PROCESS                                               
BEGIN                                                        
Reset(0) <=  '0',
'1' after 415 ns,  -- Reset the Clock
'0' after 815 ns;  

Reset(1) <=  '0',
'1' after 415 ns,  -- Reset the Decoder
'0' after 815 ns;    

Reset(2) <=  '0',
'1' after 415 ns,  -- Reset the counter
'0' after 815 ns;                  
WAIT;                                                       
END PROCESS init1; 


init2 : PROCESS                                                                                   
BEGIN                                                        
 -- Clock Generation  
 for i in 1 to num_clk_cycles loop
 CLOCK_50 <= not CLOCK_50;          
 wait for clk_period/2; 
 CLOCK_50 <= not CLOCK_50;     
 wait for clk_period/2;      
 end loop;                    
 WAIT;                                                
END PROCESS init2;                                           


init3 : PROCESS                                             

BEGIN                                                        
for j in 1 to n_cycles loop
 QAU <= not QAU;          
 wait for n_period; 
 QAU <= not QAU;     
 wait for n_period;      
 end loop;
WAIT;                                                 
END PROCESS init3;


init4 : PROCESS                                              

BEGIN                                                        
 for k in 1 to n_cycles loop
 QBU <= not QBU;          
 wait for n_period/2; 
 QBU <= not QBU;     
 wait for n_period/2;      
 end loop;
WAIT;                                                 
END PROCESS init4;  

always : PROCESS                                              
 -- optional sensitivity list                                  
 -- (        )                                                 
 -- variable declarations                                      
BEGIN                                                         
        -- -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END VHDLfinal_arch;

The loop process seems to work fine for the CLOCK_50 signal and the instructions I gave for the Reset work fine too. It's just the QAU and QBU signals not working and as a result, my Q signal which is my output.

Any reasons why?

Answer 1

Your declaration of the two stimulus signals you are having problems with look like SIGNAL QAU : STD_LOGIC;. When you perform a not on this uninitialised signal ('U'), the result is 'X'. If you declare your signal like this SIGNAL QAU : STD_LOGIC := '0';, the signal should toggle in your test bench as you expect. You are probably aware of this already, as you have done it for the CLOCK_50 signal.