Please help me to understand the need of Virtual Class in SystemVerilog.
For an abstract class, we can use Interface in SystemVerilog. What are differences between these two?
Yes, an abstract class in SystemVerilog is the same as a virtual class. Java uses the keyword 'abstract', but other languages like C++ do not have a specific keyword. SystemVerilog re-used the keyword virtual so as not to reserve another keyword. An abstract class is simply one where the constructor is protected and you cannot construct it directly, you must extend the class first and you can construct a derived object.
Abstract classes allow another concept with is a pure virtual method. These are methods that must be overridden in in the extended class. Base class libraries like the UVM are full of abstract classes and have methods that you must override, like a copy or print method.
An abstract class that only contains pure virtual methods is called an interface class and you can define an interface class that implements multiple interface classes. This years DVCon had many papers on this topic.