conversion from unsigned to integer in vhdl

Question

I'm trying to convert one signal to another type using numeric_std:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ftable is
GENERIC(      c : integer := 3;
              m : integer := 4;
              n : integer := 8;
              d : integer := 16; 
              stored_data : unsigned := x"000000010002010001010102");           
    Port ( 
              a : in unsigned (7 downto 0);
              b : in unsigned (7 downto 0);
           f_one : out  unsigned (15 downto 0);                 
           f_two : out  unsigned (15 downto 0));
end ftable;

architecture behavioral of ftable is

    signal row_id : unsigned (7 downto 0); 
    signal col_id : unsigned (7 downto 0); 
    signal r_temp : integer;
    signal c_temp : integer;

begin

    process (a, b) 
        variable addr: integer;     
    begin

        row_id <= "00000000";
        col_id <= "00000000";
        r_temp <= 0;
        c_temp <= 2;

        row_id(m  downto 0) <= b((n - 1) downto (n - (m + 1)));
        col_id(m  downto 0) <= a((n - 1) downto (n - (m + 1)));

        r_temp <= to_integer(row_id);
        c_temp <= to_integer(col_id);

        addr := d * (c * to_integer(row_id) + to_integer(col_id)) + r_temp + c_temp;
        f_one <= stored_data(addr to addr + d - 1);
        f_two <= stored_data(addr + d to addr + d + d - 1);
    end process;

end behavioral;

Code synthesizes well and when I simulate with iSim I get col_id = 00000001 and c_temp = 0 (checked in instances and processes tab).

My question is why do I get 0 instead of 1?

Edit: when simulating I also get warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

Answer 1

The std_logic values that can be converted to 0 or 1 are '0', '1', 'L', and 'h', and other values as 'U', 'X', 'Z', 'W', '-' which are called metavalues.

If any of these metavalues are in the std_logic_vector that is converted with to_integer, then 0 is returned together with the warning you see.

Problem is also that the process is only sensitive to a and b, but should include all signals that are read e.g. also col_id in order to re-execute the process when any of the intermediate signals are changed. So add all signal read in the process to the sensitivity list, or for VHDL-2008 use process (all).