Can't infer register for "RunStop" because its behavior does not match any supported register model ( Quartus II )

Question

Errors: 10821,10822...and many more..please help..(separate module)

Error (10821): HDL error at AxisCounter.vhd(48): can't infer register for "RunStop" because its behavior does not match any supported register model
Error (10821): HDL error at AxisCounter.vhd(39): can't infer register for "RunStop" because its behavior does not match any supported register model
Error (10821): HDL error at AxisCounter.vhd(38): can't infer register for "RunStop" because its behavior does not match any supported register model
Error (10822): HDL error at AxisCounter.vhd(35): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at AxisCounter.vhd(38): couldn't implement registers for assignments on this clock edge
Error (12152): Can't elaborate user hierarchy "AxisCounter:\Check:0:AxisCounter_X"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 9 warnings
Error: Peak virtual memory: 486 megabytes
Error: Processing ended: Sun May 22 18:19:32 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 9 warnings

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity AxisCounter is
    Port ( 
              BASECLK_IN      :  in   STD_LOGIC;
             START_STOP     :  in   STD_LOGIC;
             RESET_COUNT        :  in   STD_LOGIC;
              DIVISOR           :  in   Integer ;
              STEPS             :  in   Integer ;
             COUNT_STATUS   :  out  STD_LOGIC;
           AXISCLK_OUT      :  out  STD_LOGIC ;
              STEPSOVER         :  out  Integer);
end AxisCounter ;

architecture Behavioral of AxisCounter is
-- signals, variables and constants
   signal cnt_r         : Integer := 0 ;
   signal steps_r   : Integer := 0 ;
   signal blink_o   : std_logic := '0' ;
   signal RunStop   : std_logic := '1' ;
   --signal Compare1    : Integer := 75000000;  -- 1000000 ;
   --signal Steps1     : Integer := 12 ;

begin

  process(BASECLK_IN,RESET_COUNT,START_STOP) 
  begin
     if (START_STOP' event and START_STOP = '1') then
        RunStop <= '1';
     end if ;
    if rising_edge(BASECLK_IN) then
        if (RESET_COUNT = '0') then
            steps_r <= 0 ;
            cnt_r   <= DIVISOR ;
       elsif (RunStop = '1')then -- counter enabled
           cnt_r <= cnt_r - 1;
            if (cnt_r > (DIVISOR/2)) then
                blink_o <= '1' ;
            else
                blink_o <= '0' ;
                if (cnt_r = 0) then
                    steps_r <= steps_r + 1 ;
                    STEPSOVER <= steps_r ;
                    if (steps_r = STEPS) then
                        RunStop <= '0' ;
                    else
                        cnt_r <= DIVISOR ;
                    end if ;
                end if ;
            end if ;
        else
            blink_o <= '0' ;
        end if ;
    end if ;
  end process;


  AXISCLK_OUT <= blink_o ;
  COUNT_STATUS <= RunStop ;

end Behavioral;

Answer 1

What you are asking is for a flipflop to be created for RunStop that has to be clocked by two distinct clock signals: BASECLK_IN and START_STOP

There are multiple solutions for this problem:

1. you can define the behaviour of RunStop in such a way that it's no longer clocked by two sources

2. Create two versions of RunStop, 1 for each clock and combine them (asynchronously) at a later point.