Why it's code not compile?

Question

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity paralel_reg is
    generic ( default : positive := 4);
    port(C, notR, E: in std_logic; D: in std_logic_vector(default downto 1); 
    Q: out std_logic_vector(default downto 1)); 
end paralel_reg;

architecture paralel_reg of paralel_reg is
signal q : std_logic_vector(default downto 1);
begin
process (C, notR)
begin
    if notR = '0' then q <= (others => '0');
    else if rising_edge(C) then q <= D;  
    end if;
end process;  --# Error: COMP96_0019: paralel_register.vhd : (18, 5): Keyword "if" expected.
    --# Error: COMP96_0015: paralel_register.vhd : (18, 5): ';' expected.

process (E, q) --# Error: COMP96_0019: paralel_register.vhd : (24, 2): Keyword "end" expected.
begin
    if E = '0' then Q <= (others => '0');
    else Q <= q;        --# Error: COMP96_0019: paralel_register.vhd : (24, 2): Keyword "end" expected.
            --# Error: COMP96_0016: paralel_register.vhd : (24, 7): Design unit declaration expected.
    end if;
end process;
end paralel_reg;

# Error: COMP96_0019: paralel_register.vhd : (18, 5): Keyword "if" expected. # Error: COMP96_0015: paralel_register.vhd : (18, 5): ';' expected. # Error: COMP96_0019: paralel_register.vhd : (21, 1): Keyword "end" expected. # Error: COMP96_0019: paralel_register.vhd : (24, 2): Keyword "end" expected. # Error: COMP96_0016: paralel_register.vhd : (24, 7): Design unit declaration expected.

Answer 1

This:

process (C, notR) begin
    if notR = '0' then q <= (others => '0');
    else if rising_edge(C) then q <= D;  
    end if; end process;

should be this:

process (C, notR)
begin
    if notR = '0' then q <= (others => '0');
    elsif rising_edge(C) then q <= D;  
    end if;
end process;

The VHDL if statement has this format:

if ... then
  ...
elsif ... then
  ...
elsif ... then
  ...
else
  ...
end if;

All VHDL statements end with a semicolon. The above is one statement, which ends with end if;. VHDL statements can be embedded with in another. So, you can embedded another if statement inside an if statement and this is what you are doing if you use else if rather than elsif:

if ... then
  ...
elsif ... then
  ...
elsif ... then
  ...
else
  IF ... THEN
    ...
  ELSIF ... THEN
    ...
  ELSE 
    ...
  END IF;
end if;

Every if statement in VHDL requires an end if;. Notice that in the above, with one if statement embedded within another, there are two end ifs. So, you could have written:

process (C, notR) begin
    if notR = '0' then q <= (others => '0');
    else if rising_edge(C) then q <= D;  
    end if;
    end if; end process;

but I would always recommend elsif instead of else if because you need less end ifs.