Index overflow in VHDL std_logic_vector

Question

I have a doubt in following VHDL code regarding index overflow of len:

library ieee;
    use ieee.std_logic_1164.all;    
    use ieee.numeric_std.all;  
    package mypack is  
       subtype small_int is integer range 0 to 3;    
    end mypack;

library ieee;
    use ieee.std_logic_1164.all;    
    use ieee.numeric_std.all;    
    use work.mypack.all;   
entity top is    
   port(
        CLK        : in std_logic;    
        rst        : in std_logic;
        myPtr      : in small_int; 
        temp       : in unsigned(1 downto 0); 
        myout     : out std_logic_vector(3 downto 0));    
end entity;    

architecture rtl of top is
   signal len : std_logic_vector(3 downto 0)  := (others=>'0');         
   constant si : small_int := 1;
begin
    myout    <= len;
    process(clk,rst) begin
       if (RST='1') then
          len <= "0000";
       elsif rising_edge(CLK) then 
          len(myPtr - si) <= temp(0);         
       end if; 
    end process;    
end architecture;

What should be correct behaviour when myPtr = 0:

1. Would len(3) <= temp(0); happen?
2. Or, would there be an index over flow situation? Which means, len(3) will always remain at 0.

Thanks in advance.

Answer 1

In simulation, an out of range index value will generate an error.

In hardware, and out of range index value result in undefined operation, so any or no update may occur.