VHDL parse error, unexpected DIV

Question

I'm asked to show the number of the most pressed number on a keypad this is the only error that shows

ERROR:HDLParsers:164 - "D:/project/compartor.vhd" Line 37. parse error, unexpected DIV

and this is line 37

if Int_Key = i  then

What does the error means? And how can I solve it?

and this is the full code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
---------------------------------------------------------------

entity compartor is
port
(
Key_out : in  std_logic_vector(3 downto 0);
clk,rst: in std_logic;
Winner: out std_logic_vector (3 downto 0)    
);
end compartor;

architecture Behavioral of compartor is

Type Data is array (0 to 15) of integer;
Signal Counters:Data:=(others=>0);
Signal Max:integer;
Signal MaxPlace:integer;
Signal INT_Key:integer:=conv_integer(Key_out);


begin


process (clk,rst)
begin
if (rst='1') then
Winner<= (others=>'0');

elsif (rising_edge(clk)) then


  for i in 0 to 15 loop
     if Int_Key = i  then   
       Counters(i)<= Counters(i)+1;
     end if;
  end loop;

Max <= Counters(0);
MaxPlace <= 0;
    for i in 0 to 15 loop 
      if (Counters(i) > Max) then 
        Max <= Counters(i);
    MaxPlace <= i;
      end if;
    end loop;

end if;
end process;
Winner<= conv_std_logic_vector (MaxPlace,4);

end Behavioral;

Answer 1

Don't see reason for that specific error message, but there are other issues with the code.

The Winners output port is driven both in the process, and outside the process, thus having multiple drives, which the Xilinx synthesis tool won't accept.

The assign to INT_Key in the declaration like:

Signal INT_Key:integer:=conv_integer(Key_out);

gives INT_Key and initial value based on the Key_out input port, which is probably not what you want, so consider instead doing:

Signal INT_Key:integer;
...
INT_Key <= conv_integer(Key_out);

Note, that signal assignment with <= in the process does not make the new value available until next time the process is executed, for example in the case of Max <= Counters(0). It may be what you want, but it is a common pitfall for VHDL starters.

Even through VHDL is case insensitive, it is bad style using different casing for the same identifier, like you used INT_Key and Int_Key.

Consider indenting your code to follow the control structure; that will save you lots of debugging and make the code much more readable.

And a final suggestion, make a test bench for the design, and simulate before trying to make it run on hardware. Doing this extra simulation effort will actually make you finish earlier, not later.